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Enhanced virtual renaming scheme and deadlock prevention therefor
Enhanced virtual renaming scheme and deadlock prevention therefor
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机译:增强的虚拟重命名方案及其防死锁
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摘要
In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated-in a processor core.
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