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Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagrams
Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagrams
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机译:使用二进制决策图在现场可编程门阵列上执行贴装后功能分解的方法和装置
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摘要
A method for designing a system on a field programmable gate array (FPGA) includes using binary decision diagrams (BDDs) to perform functional decomposition on a design for the system after placement.
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