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Ethernet media access controller embedded in a programmable logic device—clock interface
Ethernet media access controller embedded in a programmable logic device—clock interface
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机译:嵌入可编程逻辑设备中的以太网媒体访问控制器-时钟接口
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摘要
A clock interface for a media access controller in a programmable logic device is described. The media access controller includes a clock generator for providing a clock signal to configured configurable routing of the programmable logic device to obtain a loaded version thereof. The loaded clock signal is provided to a clock network of the media access controller and to a delay cell of the media access controller to obtain an indication of the loading by the user instantiated design.
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