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Semiconductor integrated circuit verification method and test pattern preparation method
Semiconductor integrated circuit verification method and test pattern preparation method
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机译:半导体集成电路的验证方法及测试图案的制作方法
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摘要
In the inventive semiconductor integrated circuit verification method, based upon expected values of a signal from an integrated circuit, which are obtained by RTL verification or the like, and upon signal delay information obtained by static timing analysis (STA), expected value comparison times (strobe times) of a test pattern are extracted, or expected value verification as to whether values of an actually produced signal match the expected values is performed. In this manner, the inventive method allows the test pattern to be prepared with consideration given to variation in the LSI process, temperature, voltage and the like and to constraints of the test apparatus.
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