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Technique for improving negative potential immunity of an integrated circuit
Technique for improving negative potential immunity of an integrated circuit
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机译:用于提高集成电路的负电位抗扰度的技术
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摘要
An integrated circuit (IC) with negative potential protection includes at least one double-diffused metal-oxide semiconductor (DMOS) cell formed in a first-type epitaxial pocket, which is formed in a second-type substrate. The IC also includes a second-type+ isolation ring formed in the substrate to isolate the first-type epitaxial pocket and a first-type+ ring formed through the first-type epitaxial pocket between the second-type+ isolation ring and the DMOS cell.
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