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Hardware implementation of the secure hash standard
Hardware implementation of the secure hash standard
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机译:安全哈希标准的硬件实现
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摘要
An integrated circuit for implementing the secure hash algorithm is provided. According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller further includes an address control module and a finite state machine.
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