首页> 外国专利> MULTI-THESHOLD MESSAGE PASSING DECODING OF LOW DENSITY PARITY CHECK CODES USING THE MIN-SUM PRINCIPLE

MULTI-THESHOLD MESSAGE PASSING DECODING OF LOW DENSITY PARITY CHECK CODES USING THE MIN-SUM PRINCIPLE

机译:基于最小和原理的低密度奇偶校验码的多阈值消息通过解码

摘要

A message-passing decoder for low-density parity-check codes (LDPC) is provided using a multi-value threshold scheme which is updated throughout the decoding iterations. In an embodiment the check node processing is implemented using the min-sum principle whereby for each corresponding row of the parity check matrix a first and a second minimum value among bit reliability values is determined. Each row of the decoder comprises one or more associative processing elements controlled by a row control element to determine the two minimum values. Each column comprises one or more associative processing elements, an input processing element, and a column control element to determine hard decision bits. The usage of processing elements to construct a decoder may reduce the gate count and decrease the interconnects used to couple the elements.
机译:使用多值阈值方案提供了用于低密度奇偶校验码(LDPC)的消息传递解码器,该方案在整个解码迭代过程中都会更新。在一个实施例中,使用最小和原理来实现校验节点处理,由此对于奇偶校验矩阵的每个对应行,确定比特可靠性值之中的第一和第二最小值。解码器的每一行包括一个或多个相关处理元件,该相关处理元件由行控制元件控制以确定两个最小值。每一列包括一个或多个关联处理元件,输入处理元件和确定硬判决位的列控制元件。使用处理元件来构造解码器可以减少门数量并减少用于耦合元件的互连。

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