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BUFFER AMPLIFIER, DRIVER IC, AND DISPLAY APPARATUS USING THAT DRIVER IC

机译:缓冲放大器,驱动器IC以及使用该驱动器IC的显示装置

摘要

A buffer circuit is driven with a low voltage and operates at a high speed has first and second comparators constituted by P channel and N channel MOS transistors provided between an input terminal and an output terminal of a buffer amplifier. A predetermined offset voltage is set for the comparing operation, and a switch circuit turns ON/OFF in response to an output signal from the first comparator and the output signal of the second comparator. A leading up of an output voltage from the buffer amplifier is accelerated by the current flowing from a power source line to the output terminal. The buffer circuit also includes an operation restricting circuit for restricting the comparing operation of the second comparator in a range of a dead band of the transistors.
机译:缓冲电路以低电压驱动并且以高速度操作,具有由设置在缓冲放大器的输入端子和输出端子之间的P沟道和N沟道MOS晶体管构成的第一和第二比较器。为比较操作设置预定的偏移电压,并且开关电路响应于来自第一比较器的输出信号和第二比较器的输出信号而接通/断开。从电源线流向输出端子的电流加速了缓冲放大器的输出电压的上升。缓冲电路还包括用于在晶体管的死区范围内限制第二比较器的比较操作的操作限制电路。

著录项

  • 公开/公告号KR100872920B1

    专利类型

  • 公开/公告日2008-12-08

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20077005695

  • 发明设计人 이노꾸찌 히로유끼;

    申请日2007-03-12

  • 分类号H03F3/50;H03F1/56;H03K19/0175;

  • 国家 KR

  • 入库时间 2022-08-21 19:14:22

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