A Method for Synthesizing System-on-Chip Communication Architecture

摘要

A method for synthesizing a system-on-chip communication architecture is provided to enhance communication performance and to reduce an occupied area when a result from generation of an on-chip network topology is compared with a conventional on-chip bus design result or on-network implementation result. A method for synthesizing a system-on-chip communication architecture comprises the following several steps. A reference code where a design specification of an algorithm step is implemented is performed, a communication requirement amount among IP modules is analyzed and a traffic graph is generated(110). On the basis of the traffic graph, a binary tree where the IP modules are children nodes at the lowest level(120). Intermediate nodes of the binary tree are merged and the binary tree is optimized for minimizing a delay time or an occupied area among the IP modules(130). Direct paths are inserted among the IP modules which have critical paths among them(140). A communication parallel property graph is constructed for obtaining the maximum communication parallel property of each merged intermediate node(150). On the basis of the communication parallel property graph, a communication configuration type with respect to each merged intermediate node is determined(160). A communication configuration type of upper level intermediate nodes which connects the merged intermediate nodes to one another and are positioned at a level higher than the merged intermediate nodes is determined(170).