首页> 外国专利> almost orthogonal befehlsatz architecture for a dual multiplizierer - akkumulierer with a minimum of kodierbits

almost orthogonal befehlsatz architecture for a dual multiplizierer - akkumulierer with a minimum of kodierbits

机译:具有最小编码位的双乘法器-累加器的几乎正交的指令集架构

摘要

A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set. IMAGE
机译:提供了近正交的双MAC指令集,该指令集实际上仅使用65个命令即可实现272个命令的正交指令集的全部功能。通过消除基于相对于命令结果的对称性的指令并通过施加与项目有关的简单限制(例如,程序员的数据呈现顺序)来实现减少的指令集。命令的特定选择还由与双MAC架构关联的双字对齐存储器架构确定。精简的指令集体系结构保留了命令集的功能和固有的并行性,并且与完整的正交集相比,所需的命令位更少。 <图像>

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号