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almost orthogonal befehlsatz architecture for a dual multiplizierer - akkumulierer with a minimum of kodierbits
almost orthogonal befehlsatz architecture for a dual multiplizierer - akkumulierer with a minimum of kodierbits
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机译:具有最小编码位的双乘法器-累加器的几乎正交的指令集架构
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摘要
A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the result of the commands and by imposing simple restrictions related to items such as the order of data presentation by the programmer. Specific selections of commands are also determined by the double word aligned memory architecture which is associated with the dual-MAC architecture. The reduced instruction set architecture preserves the functionality and inherent parallelism of the command set and requires fewer command bits to implement than the full orthogonal set. IMAGE
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