Processor for CPU, has hardware sequencer managing running of tasks and providing instruction for giving control to sequencer at end of tasks, where instruction sets program with base address relative to next task to program counter

摘要

The processor (9) has a hardware sequencer (5) managing running of tasks. A primary instruction is provided for writing a base address or a value relative to a next task to be executed in a program counter (8) and for reading the value from a register (4) i.e. First in first out type memory. A secondary instruction is provided for writing the value in a register (6), and for giving control to the sequencer at end of the tasks, where the secondary instruction sets a program with the address of the next task to the counter.