Suppressing power supply noise using an LFSR pseudo random scrambling process

摘要

An integrated circuit comprises a transmit data path, for transmitting data to one or more dynamic random access memory devices, which includes scrambling logic to generate, in parallel, N uncorrelated pseudo random outputs. The data to be transmitted, having M bits, and the pseudo random outputs are input to XOR logic so that M scrambled bits are output in parallel. Thus the scrambled output has a substantially white frequency spectrum. The scrambling logic uses a linear feedback shift register (LFSR) wherein the seed, which could itself be scrambled before use, is based on the memory address e.g. the column address. The polynomial used for the LFSR could be X16+X13+X10+X9+X8+X4+1. This scrambling method could be used to suppress power supply noise in, for example, double data rate (DDR) memory systems.