Logic basic cell is provided for logically combining the second input signal and the first input signal for the logic subfunction second, the second logic function block and the first logic function block, or the first that can be predetermined have. Also, the logic basic cell is provided with a first logic transistor having a source / drain terminal and a gate terminal coupled to the first logic function block. Third input signal can be supplied to the gate terminal. In the source / drain terminal, the output signal can be supplied. Moreover, the second logic transistor is coupled to a second logic function block, a source / drain terminal and a gate terminal are provided. In the gate terminal, complementary signals can be supplied to the third input signal. The source / drain terminal is coupled to the source / drain terminal of the first logic transistor.
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