The advanced RAID6 system architecture due to pattern matching

摘要

The acceleration section which lightens the calculation load which is concentrated on the processor is offered. Two data processing routes where as for the acceleration section, each has logical operation unit, shares the single multiplier are had. Setting possible operation in parallel, vis-a-vis the same data to do it is possible each data processing route. With single pass of the data which minds the acceleration section, the special multiplier and the order which reaches the point where it can calculate P and the Q syndrome in the stripe are offered. Selective figure Figure 1