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Terminal formation method of lamination type package element and lamination type package element, formation method of lamination type package, and lamination type package

机译:层叠型封装元件和层叠型封装元件的端子形成方法,层叠型封装的形成方法和层叠型封装

摘要

The semiconductor chip module whose degree of freedom of position of the terminal for connection of allotment and each semiconductor chip of circuit to each semiconductor chip is high is offered. As for this invention, portion of the terminal for connection which is connected with the circuit pattern which is provided on the surface is provided on the side, superposing the plural semiconductor chips, it regards the semiconductor chip module which it connects. The terminal part for connection side in each semiconductor chip, is connected mutually by wiring pattern. The terminal for connection in the semiconductor chip is something which reaches to the side from the surface, applying the fact that it sprays the electric conduction material in mist condition is something which was formed.
机译:提供一种半导体芯片模块,该半导体芯片模块的用于分配的端子和电路的每个半导体芯片的连接的位置自由度高。对于本发明,连接用端子的与设置在表面上的电路图案相连接的部分设置在侧面,该多个叠置的半导体芯片相互叠置,被视为连接的半导体芯片模块。各半导体芯片中的连接侧的端子部通过配线图案相互连接。半导体芯片中用于连接的端子是从表面延伸到侧面的东西,这是因为它以雾状喷射导电材料这一事实已经形成。

著录项

  • 公开/公告号JPWO2008114430A1

    专利类型

  • 公开/公告日2010-07-01

    原文格式PDF

  • 申请/专利权人 株式会社日本マイクロニクス;

    申请/专利号JP20090505029

  • 发明设计人 池田 真人;

    申请日2007-03-20

  • 分类号H01L23/52;H01L25/065;H01L25/07;H01L25/18;

  • 国家 JP

  • 入库时间 2022-08-21 18:57:26

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