Logic circuit design apparatus, logic circuit design method and logic circuit design program for asynchronous logic circuit

摘要

An object of the present invention is to provide a logic circuit design apparatus for designing an asynchronous logic circuit that satisfies the characteristic constraints of a state memory element represented by a latch or flip-flop. A signal transition sequence for generating a control signal pulse of a state memory element is extracted from a state transition graph input to a logic circuit design device by a state memory control signal transition sequence extraction unit 112, and a pulse generation path delay constraint setting is added. The unit 115 performs logic synthesis by setting the minimum delay constraint of the signal line path corresponding to the signal transition sequence as the minimum pulse width constraint value of the state storage element.