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METHOD AND SYSTEM FOR GENERATING AN INTEGRATED CIRCUIT CHIP FACILITY WAVEFORM FROM A SERIES OF CHIP SNAPSHOTS
METHOD AND SYSTEM FOR GENERATING AN INTEGRATED CIRCUIT CHIP FACILITY WAVEFORM FROM A SERIES OF CHIP SNAPSHOTS
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机译:从一系列芯片快照中生成集成电路芯片设施波形的方法和系统
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摘要
Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.
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