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CYCLIC CODE PROCESSING CIRCUIT, NETWORK INTERFACE CARD, AND CYCLIC CODE PROCESSING METHOD

机译:循环代码处理电路,网络接口卡和循环代码处理方法

摘要

Processor 23 calculates a first remainder, which is a remainder produced when an integral multiple data block is divided by a generator poly-nomial, by processing bits represented by the number of parallel bits in parallel. The integral multiple data block comprises bits positioned closer to the leading end of the input data than a final word which is a word at the tail end of the input data, in the case where a plurality of bits making up the input data are successively divided from the leading end with respect to each word which comprises the bits represented by the number of parallel bits. Processor 23 calculates a second remainder, which is a remainder produced when a final word valid data block made up of bits of the input data other than the integral multiple data block is divided by the generator polynomial. Processor 23 calculates an input data remainder, which is a remainder produced when the input data are divided by the generator polynomial, based on the first remainder and the second remainder.
机译:处理器 23 通过处理由并行并行位数表示的比特,计算出第一余数,该整数是将整数倍数据块除以生成多项式而产生的余数。在构成输入数据的多个位被相继划分的情况下,整数倍数据块包括比作为输入数据的尾端的单词的最终单词更靠近输入数据的前端的位。相对于包含由并行位数表示的位数的每个单词,从开头到末尾。处理器 23 计算第二余数,该余数是当由除整数倍数数据块之外的输入数据的位组成的最终字有效数据块被生成多项式除时产生的余数。处理器 23 基于第一余数和第二余数,计算输入数据余数,该余数是在将输入数据除以生成多项式后所产生的余数。

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