Field Programmable Logic Arrays (FPGAs) are described which utilize multiple power supply voltages to reduce both dynamic power and leakage power without sacrificing speed or substantially increasing device area. Power reduction mechanisms are described for numerous portions of the FPGA, including logic blocks, routing circuits, connection blocks, switch blocks, configuration memory cells, and so forth. Embodiments describe circuits and methods for implementing multiple supplies as sources of Vdd, multiple voltage thresholding Vt, signal level translators, and power gating of circuitry to deactivate portions of the circuit which are inactive. The supply voltage levels can be fixed, or programmable. Methods are described for performing circuit CAD in the routing and assignment process on FPGAs, in particular for optimizing FPGA use having the power reduction circuits taught. Routing methods describe utilizing slack timing, power sensitivity, trace-based simulations, and other techniques to optimize circuit utilization on a multi Vdd FPGA.
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机译：描述了现场可编程逻辑阵列（FPGA），其利用多个电源电压来减小动态功率和泄漏功率两者，而不牺牲速度或实质上不增加器件面积。描述了针对FPGA众多部分的功耗降低机制，包括逻辑块，路由电路，连接块，开关块，配置存储单元等。实施例描述了用于将多个电源实现为V dd 的源，多个电压阈值V t ，信号电平转换器以及电路的功率门控以停用电路的部分的电路和方法。处于非活动状态。电源电压电平可以是固定的，也可以是可编程的。描述了用于在FPGA上的路由和分配过程中执行电路CAD的方法，特别是用于优化具有所教导的功率降低电路的FPGA使用的方法。路由方法描述了利用松弛时序，功率灵敏度，基于轨迹的仿真和其他技术来优化多V dd FPGA上的电路利用率。
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