首页> 外国专利> HYBRID CONDUCTIVE VIAS INCLUDING SMALL DIMENSION ACTIVE SURFACE ENDS AND LARGER DIMENSION BACK SIDE ENDS, SEMICONDUCTOR DEVICES INCLUDING THE SAME, AND ASSOCIATED METHODS

HYBRID CONDUCTIVE VIAS INCLUDING SMALL DIMENSION ACTIVE SURFACE ENDS AND LARGER DIMENSION BACK SIDE ENDS, SEMICONDUCTOR DEVICES INCLUDING THE SAME, AND ASSOCIATED METHODS

机译:混合导电通孔,包括小尺寸有源表面端和较大尺寸的后端,包括相同器件的半导体器件以及相关方法

摘要

A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed.
机译:半导体器件的导电通孔包括延伸到制造基板的有源表面中的相对较小直径的部分和延伸到制造基板的背面中的相应的相对较大直径的部分。可以通过在BEOL处理之前或期间形成相对较小直径的部分来制造这种类型的导电通孔,而可以在完成BEOL处理之后制造每个导电通孔的大直径部分。还公开了包括具有这种导电通孔的一个或多个半导体器件的电子器件。

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