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System for increasing the speed of a sum-of-absolute-differences operation
System for increasing the speed of a sum-of-absolute-differences operation
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机译:用于提高绝对差之和运算速度的系统
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摘要
An adaptation of the sum-of-absolute-differences (SAD) calculation is implemented by modifying existing circuitry in a microprocessor. The adaptation yields a reduction of over 30% for a current SAD calculation. The adaptation includes a first and second operand register, each storing respectively a first and second set of 2's complement binary data, an arithmetic logic unit (ALU), and a destination register. An add/subtract enable input on the ALU receives a most significant bit (MSB) of the second set of binary data. The ALU adds the first and second data sets if the MSB is a “0” and subtracts the second data set from the first data set if the MSB is a “1.” The add/subtract enable input has the effect of taking the absolute value of the second data set without having to first perform an absolute value determination, thus eliminating processing steps.
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