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Dual Current Path LDMOSFET with Graded PBL for Ultra High Voltage Smart Power Applications
Dual Current Path LDMOSFET with Graded PBL for Ultra High Voltage Smart Power Applications
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机译:具有分级PBL的双电流路径LDMOSFET,适用于超高压智能电源应用
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摘要
A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed adjacent to the source region (412) to define a first channel region (107), and a current routing structure that includes a buried RESURF layer (408) in ohmic contact with a second well region (414) formed in a predetermined upper region of the epitaxial layer (404) so as to be completely covered by the gate electrode (420), the current routing structure being spaced apart from the first well region (406) and from the drain region (416) on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.
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