Semiconductor memory device having output impedance adjustment circuit and test method of output impedance

摘要

A semiconductor device has an output impedance adjustment circuit for automatically adjusting an output impedance of an output circuit including transistors connected in parallel. The output impedance adjustment circuit includes: a replica circuit including a circuit portion of the substantially same configuration as the output circuit; a comparator for comparing a magnitude of the output impedance of the replica circuit with a reference resistor and for outputting a comparison result as an internal counter control signal; a switching controller selectively switching between an external counter control signal from outside and the internal counter control signal; and a counter circuit for performing a count operation selectively according to the internal or the external counter control signal and for outputting a count value as an adjustment code which is supplied to the output circuit and the replica circuit so that each transistor is controlled to be on/off based on the adjustment code.