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Microprocessor instruction execution method for exploiting parallelism by time ordering operations in a single thread at compile time
Microprocessor instruction execution method for exploiting parallelism by time ordering operations in a single thread at compile time
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机译:用于在编译时通过单线程中的时间排序操作利用并行性的微处理器指令执行方法
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摘要
A low overhead mechanism for supporting speculative execution and code compression in a Very Long Instruction Word (VLIW) microprocessor. Profitable speculations can be determined statically at compile time and a low overhead hardware recovery mechanism used that does not require compensation code.
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