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Asymmetric rise/fall time and duty cycle control circuit

机译:非对称上升/下降时间和占空比控制电路

摘要

Modules and signal control circuits configured to at least partially compensate for or adjust for asymmetric rise/fall time. The circuit may include a first input node configured to receive a first data signal and a second input node configured to receive a second data signal that is complementary of the first data signal. The circuit may also include a first stage having a first node coupled to the first input node and a second node coupled to the second input node and a second stage having a first node coupled to a third node of the first stage and a second node coupled to a fourth node of the first stage. The second stage may be configured to drive a load such as a laser. The circuit may further include a third input node configured to receive a third data signal and a fourth input node configured to receive a fourth data signal that is the complementary of the third data signal. Additionally, a control stage having a first node coupled the third input node, having a second node coupled to the fourth input node, having a third node coupled to the third node of the first stage and having a fourth node coupled to the fourth node of the first stage.
机译:被配置为至少部分地补偿或调整非对称上升/下降时间的模块和信号控制电路。该电路可以包括被配置为接收第一数据信号的第一输入节点和被配置为接收与第一数据信号互补的第二数据信号的第二输入节点。该电路还可以包括第一级,第二级的第一节点耦合到第一输入节点,第二节点耦合到第二输入节点,第二级具有第一节点,第一节点耦合到第一级的第三节点,第二节点耦合到第一阶段的第四个节点。第二级可以被配置为驱动诸如激光器的负载。该电路可以进一步包括被配置为接收第三数据信号的第三输入节点和被配置为接收作为第三数据信号的互补的第四数据信号的第四输入节点。另外,控制级具有第一节点耦合到第三输入节点,第二节点耦合到第四输入节点,第三节点耦合到第一级的第三节点,第四节点耦合到第一级的第三节点。第一阶段。

著录项

  • 公开/公告号US7764885B2

    专利类型

  • 公开/公告日2010-07-27

    原文格式PDF

  • 申请/专利权人 THELINH NGUYEN;TIMOTHY G. MORAN;

    申请/专利号US20070626081

  • 发明设计人 TIMOTHY G. MORAN;THELINH NGUYEN;

    申请日2007-01-23

  • 分类号H04B10/00;

  • 国家 US

  • 入库时间 2022-08-21 18:50:00

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