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Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array
Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array
A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.
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