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High performance raid-6 system architecture with pattern matching
High performance raid-6 system architecture with pattern matching
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机译:具有模式匹配功能的高性能RAID-6系统架构
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摘要
An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.
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