首页> 外国专利> Communications bus having low latency interrupts and control signals, hotpluggability error detection and recovery, bandwidth allocation, network integrity verification, protocol tunneling and discoverability features

Communications bus having low latency interrupts and control signals, hotpluggability error detection and recovery, bandwidth allocation, network integrity verification, protocol tunneling and discoverability features

机译:具有低延迟中断和控制信号,热插拔性错误检测和恢复,带宽分配,网络完整性验证,协议隧道和可发现性功能的通信总线

摘要

Disclosed are methods and apparatus to control data and command flow over a physical communications channel between a transmitter and a receiver, and more specifically to provide a protocol for a point-to-point serial bus architecture with low latency time for flow control and other signaling, regardless of the length of the data packet frame. The abstract data flow control protocol can be employed by various buses as it interacts only with the lowest protocol layers. Separate buffers for data and control can be used to allow the bus to be compatible with slower buses also to support additional control functions without involving a higher protocol layer.
机译:公开了用于控制在发射机和接收机之间的物理通信信道上的数据和命令流的方法和装置,并且更具体地,提供用于点对点串行总线体系结构的协议,该协议具有用于流控制和其他信令的低等待时间。 ,而不考虑数据包帧的长度。抽象数据流控制协议可以被各种总线使用,因为它仅与最低的协议层进行交互。可以使用用于数据和控制的单独缓冲区使总线与较慢的总线兼容,也可以在不涉及更高协议层的情况下支持其他控制功能。

著录项

  • 公开/公告号US7668202B2

    专利类型

  • 公开/公告日2010-02-23

    原文格式PDF

  • 申请/专利权人 MICHEL GILLET;

    申请/专利号US20040961366

  • 发明设计人 MICHEL GILLET;

    申请日2004-10-07

  • 分类号H04J3/16;

  • 国家 US

  • 入库时间 2022-08-21 18:48:46

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