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High-speed interface for high-density flash with two levels of pipelined cache
High-speed interface for high-density flash with two levels of pipelined cache
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机译:具有两级流水线式高速缓存的高速接口,用于高密度闪存
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摘要
A memory circuit and a method of operating a flash or EEPROM device that has two levels of internal cache. A memory device having a memory array, sense amplifiers, a data register, cache, an input-output circuit, and a control logic circuit is configured to output data while simultaneously reading data from the memory array to the data register or simultaneously copying data from the data register to a first level of internal cache. In addition, the memory device is configured to output data while simultaneously writing data from the data register to the memory array.
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