Agile clock mechanism and method for ultrawide bandwidth communications system

摘要

An ultra wide bandwidth communications system, method and computer program product including an ultra wide bandwidth timing generator. The timing generator includes a high frequency clock generation circuit having low phase noise; a low frequency control generation circuit; and a modulation circuit coupled between the high frequency clock generation circuit and the low frequency control generation circuit. The high frequency clock generation circuit generates a plurality of high frequency clock signals. The low frequency control generation circuit generates a plurality of low frequency control signals. The modulation circuit modulates the high frequency clock signals with the low frequency control signals to produce an agile timing signal at a predetermined frequency and phase. The agile timing signal is generated at the predetermined frequency and phase by adjustments to at least one of frequency of the low frequency control signals, phase of the low frequency control signals, frequency of the high frequency clock signals, and phase of the high frequency clock signals.