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Fault tolerant system and controller, operation method, and operation program used in the fault tolerant system

机译:容错系统和控制器,用于该容错系统的操作方法和操作程序

摘要

There is provided a fault tolerant system capable of adequately performing error processing, synchronization processing, and resynchronization processing for realizing a fault tolerant function in accordance with the system state. The fault tolerant system comprises at least two systems including: a CPU subsystem; an IO subsystem connected to the CPU subsystem; an FT controller to be connected between the CPU subsystem and 10 subsystem; and crosslinks connecting own system and other system through the FT controller. The CPU subsystem operates at the same timing with a CPU subsystem of other system in lock-step. The FT controller manages a plurality of system operations, according to which both systems perform error processing, duplication processing, and resynchronization processing for fault tolerant, by associating a plurality of states corresponding to the system operations with predetermined event signals. According to these event signals, the FT controller selects the system operations while changing the states for every system and allows the CPU subsystem to perform the selected system operation.
机译:提供了一种容错系统,其能够适当地执行错误处理,同步处理和再同步处理,以根据系统状态来实现容错功能。容错系统包括至少两个系统,其包括:CPU子系统;以及连接到CPU子系统的IO子系统;一个FT控制器连接在CPU子系统和10个子系统之间;以及通过FT控制器连接本系统和其他系统的交叉链接。 CPU子系统在锁定步骤中与其他系统的CPU子系统在相同的时间运行。 FT控制器管理多个系统操作,根据该系统,两个系统通过将与系统操作相对应的多个状态与预定事件信号相关联来执行用于容错的错误处理,复制处理和再同步处理。根据这些事件信号,FT控制器在更改每个系统的状态的同时选择系统操作,并允许CPU子系统执行所选的系统操作。

著录项

  • 公开/公告号EP1675003A3

    专利类型

  • 公开/公告日2010-02-24

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号EP20050027906

  • 发明设计人 MIZUTANI FUMITOSHI;

    申请日2005-12-20

  • 分类号G06F11/16;

  • 国家 EP

  • 入库时间 2022-08-21 18:39:27

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