首页> 外国专利> Floating point unit-processing elementFPU-PE structure, reconfigurable array processorRAP comprising the same FPU-PE structure, and multi-media platform comprising the same RAP

Floating point unit-processing elementFPU-PE structure, reconfigurable array processorRAP comprising the same FPU-PE structure, and multi-media platform comprising the same RAP

机译:浮点单元处理元素FPU-PE结构,包含相同FPU-PE结构的可重新配置阵列处理器RAP和包含相同RAP的多媒体平台

摘要

The present invention provides a relatively fast a size almost similar hardware floating point operations while the reconfiguration of the conventional array structure can be carried out, low-power and price reconstruction array processor having a high performance ratio characteristic (Reconfigurable Array Processor), and provides a multimedia platform, including the processor. The reconstruction array processor at least two integer operation processing elements (processing element: PE) floating point unit made by combining the (Floating-Point Unit: FPU) -PE are arranged a plurality of the PE array (array); Context for controlling the communication of data between each row or column of PE and PE the PE array operations (context) which is stored the configuration cache (Configurable Cache); And the PE array, the cache memory of a frame buffer to store the intermediate result of (Frame buffer);., And include, the FPU-PE using a floating-point (floating point) operations can be performed
机译:本发明提供了相对快的,大小几乎相似的硬件浮点运算,同时可以进行常规阵列结构的重构,具有高性能比特性的低功耗和价格重构阵列处理器(Reconfigurable Array Processor),并提供多媒体平台,包括处理器。重构阵列处理器将至少两个整数运算处理元件(处理元件:PE)通过组合(Floating-Point Unit:FPU)-PE制成的浮点单元排列多个PE阵列(array);用于控制PE的每一行或每一列与PE之间的数据通信的上下文,以及PE阵列操作(上下文),该操作存储在配置缓存(Configurable Cache)中;并且,PE阵列,帧缓冲器的高速缓冲存储器用于存储(帧缓冲器)的中间结果;并且包括,可以执行使用浮点(Floating point)操作的FPU-PE

著录项

  • 公开/公告号KR100948512B1

    专利类型

  • 公开/公告日2010-03-25

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20080090012

  • 发明设计人 양훈모;최기영;박일현;조만휘;

    申请日2008-09-11

  • 分类号G06F7/483;G06F7/57;G06F9/30;

  • 国家 KR

  • 入库时间 2022-08-21 18:31:26

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