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METHOD AND SYSTEM FOR DESIGNING, SIMULATING AND DEBUGGING DIGITAL INTEGRATED CIRCUIT USING PROCEDURAL HIGH LEVEL PROGRAMMING LANGUAGES

机译:使用过程级高级编程语言设计,模拟和调试数字集成电路的方法和系统

摘要

PURPOSE: A digital integrated circuit design, a simulation, a verifying method and a system thereof using procedural high level programming languages is provided to easily implement the error detection and correction process by shortening the simulation time. CONSTITUTION: At least one clock edge among edges of more than one clocks is activated based on a sequence appearing on each clock edge(S21). Output variables of all the registers are updated b value of input variables of every registers(S22). The calculation language of logics is sequentially executed(S23). The calculation result value is stored on an input variable of each register connected to each logic, or discarded(S24).
机译:目的:提供一种使用程序高级编程语言的数字集成电路设计,仿真,验证方法及其系统,以通过缩短仿真时间轻松实现错误检测和纠正过程。构成:一个以上时钟沿中的至少一个时钟沿是根据每个时钟沿上出现的顺序激活的(S21)。通过每个寄存器的输入变量的值更新所有寄存器的输出变量(S22)。逻辑的计算语言被顺序执行(S23)。计算结果值被存储在与每个逻辑连接的每个寄存器的输入变量上,或者被丢弃(S24)。

著录项

  • 公开/公告号KR100965856B1

    专利类型

  • 公开/公告日2010-06-24

    原文格式PDF

  • 申请/专利权人 MODEMGATE CO. LTD.;

    申请/专利号KR20090119547

  • 发明设计人 OH JERRY JOUNGHEON;

    申请日2009-12-04

  • 分类号G01R31/28;G06F17/50;

  • 国家 KR

  • 入库时间 2022-08-21 18:31:05

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