Testing device (10) for testing a test device (100), comprising:a signal input circuit (26), the a phase of a test signal in accordance with a by means of a phase control circuit (56) with respect to a phase of a reference signal value which is of a shift amount shifts and the phase-shifted test signal in, the tested device (100) inputs;a device evaluation circuit (32), the, the tested device (100) is evaluated on the basis of a determination of the tested device (100) in response to the input test signal output signal; anda shift amount - measuring circuit (36), the a phase displacement amount of the of the signal input circuit (26) to test signal output a synchronization signal which is synchronized with the reference signal, that is shift amount - measuring circuit (36) contains:a first loop circuit (42), which generates the synchronization signal;a clock data recovery circuit - again cdr (46), which provides a first control signal in the first loop circuit (42), which has a value of the according to a phase difference between the synchronization signal and the test signal is determined, by a predetermined phase difference between the synchronization signal..
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