spannungspuffer for large gate loads over the entire versorgungsspannungsbereich and preferential use in voltage regulator with small verlustspannung

摘要

Described is a low-dropout (LDO) voltage buffer implemented in CMOS with nearly rail-to-rail in/output operation which is capable of driving a large MOS gate. The voltage buffer utilizes a single mismatched input transistor pair with systematic offset which is biased to 350 mV below Vdd to operate at a reduced threshold voltage by utilizing the backgate effect (body effect). A dynamic biasing circuit is coupled to the input transistor pair to get high current efficiency. Reduced biasing to restore the full threshold voltage is achieved by shorting out resistive means coupled between the common bulk of the input transistor pair and the common bulk of the biasing circuit. IMAGE