An integrated circuit 8 comprising an array 10 of interconnected configurable logic elements 12, such as an FPGA, is provided. The array is divided into a plurality of regions each of which contains one or more logic elements. Each of the logic elements processes data according to a configuration stored in the logic element. One or more of the logic elements are configured to form a power controller 14 which separately controls the power state of different regions of the array. Each region has a corresponding region controller 16 responsive to one or more power signals generated by the power controller to switch that region into the requested power state. The power states can include a powered state, an unpowered state, a configuration-retention state, a state-retention state, a clocked state, an unclocked state, a divided-clock state and a selected-clock state. Alternatively the power states can include a plurality of voltage states comprising the supply of a given voltage level to logic elements within a region. Clock signals may be provided to the array with a clock tree comprising separate clock tree branches for each region. The power controller may base the power control signals upon power state demands of logic elements within a region or a power requirement signal supplied from the region.
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