The static electricity discharge protection network conservation the protection network and its

摘要

ESD protection circuit for use with high-voltage resistance I / O circuits of an IC and is (201). This circuit, boost voltage bus relatively small from the I / O pad: can be realized by providing ESD diode small to (BOOST bus) and (217). With this boost bus, power is supplied to the trigger circuit (203). Current consumption of the trigger circuit is a minimum current flowing through the path during an ESD is very little. Voltage of the diode drops but, IR voltage drop trigger circuit (203) requires only slightly from the I / O pad. I want to control (207, 209)-type clamp NMOSFET of cascaded (203) is relatively large trigger circuit. Ultimately, both gates of the clamp type NMOSFET - (VGS) is enhanced source voltage, conductivity type clamp NMOSFET which are cascaded (207, 209) increases. Thus, the on resistances of the NMOSFET (207, 209) is reduced, thus ESD performance is improved, the layout area required to implement robust ESD protection circuit is reduced.