首页> 外国专利> Fault verification manner of the logical system, being fault verification manner of the fault verification device which

Fault verification manner of the logical system, being fault verification manner of the fault verification device which

机译:逻辑系统的故障验证方式,为故障验证装置的故障验证方式,

摘要

PPROBLEM TO BE SOLVED: To provide a technique for efficiently finding out a failure occurrence condition in verification of a black box of a logic system comprising hardware and software. PSOLUTION: The verification device for clarifying the failure occurrence condition acquires each combination failure occurrence probability index and a verified combination failure occurrence integrated value for verified test items of the logic system, further acquires a combination failure occurrence integrated value of each unverified test item of the logic system, and extracts an unverified test item in which the unverified test item combination failure occurrence integrated value is closest to a value obtained by multiplying the verified combination failure occurrence integrated value by a certain ratio factor as the next verification object. PCOPYRIGHT: (C)2008,JPO&INPIT
机译:

要解决的问题:提供一种用于在验证包括硬件和软件的逻辑系统的黑匣子时有效地找出故障发生条件的技术。

解决方案:用于澄清故障发生条件的验证装置获取每个组合故障发生概率指标和逻辑系统的已验证测试项目的已验证组合故障发生积分值,还获取每个未验证测试的组合故障发生积分值然后,提取未验证的测试项目,其中未验证的测试项目组合失败发生累计值最接近通过将验证的组合失败发生累计值乘以一定的比例因子而获得的值作为下一个验证对象。

版权:(C)2008,日本特许厅&INPIT

著录项

  • 公开/公告号JP4631858B2

    专利类型

  • 公开/公告日2011-02-23

    原文格式PDF

  • 申请/专利权人

    申请/专利号JP20070033246

  • 发明设计人

    申请日2007-02-14

  • 分类号G06F11/22;G06F11/28;

  • 国家 JP

  • 入库时间 2022-08-21 18:20:35

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