Support for multiple outstanding requests to multiple targets in a pipelined memory system

摘要

One embodiment of the present invention provides an apparatus (152) that supports multiple outstanding load and/or store requests from an execution engine (106, 108) to multiple sources of data in a computer system. This apparatus includes a load store unit (102, 104) coupled to the execution engine (106, 108), a first data source (114) and a second data source (144, 146, 148, 150). This load store unit (102) includes a load address buffer (216), which contains addresses for multiple outstanding load requests. The load store unit (102) also includes a controller (250) that co-ordinates data flow between the load address buffer (216), a register file (110), the first data source and the second data source (144, 146, 148, 150) so that multiple load requests can simultaneously be outstanding for both the first data source and the second data source. These load requests return in-order for each of the multiple sources of data in the computer system, except for load requests directed to a data cache (114) which can return out-of-order. Load requests may return out-of-order with respect to load requests from other data sources. According to one aspect of the present invention, the load store unit (102) additionally includes a store address buffer (220), that contains addresses for multiple outstanding store requests, and a store data buffer (230) that contains data for the multiple outstanding store requests. The controller (250) is further configured to co-ordinate data flow between the first data source, the second data source, the store address buffer (220) and the store data buffer (230), so that multiple store requests can simultaneously be outstanding for both the first data source and the second data source. IMAGE