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FAST REPEATER LATCH

机译:快修门闩

摘要

A repeater circuit is disclosed. The repeater circuit includes an input circuit coupled to receive a data input signal and a clock signal, and an output circuit configured to, when activated, drive an output signal on an output node. The input circuit is further configured to activate the output circuit in order to initiate a logical transition of the data output signal. A deactivation circuit is configured to deactivate the output circuit at a delay subsequent to activation. A latch is coupled the output circuit and it is configured to change a latch output state responsive to activation of the output circuit. The latch is configured to hold a state the output node subsequent to deactivation of the output circuit. The input circuit is configured to activate the output circuit dependent on the clock signal. The deactivation circuit is configured to deactivate the output circuit independent of the clock signal.
机译:公开了一种中继器电路。所述转发器电路包括:输入电路,被耦合为接收数据输入信号和时钟信号;以及输出电路,被配置为在被激活时驱动输出节点上的输出信号。输入电路还被配置为激活输出电路,以便启动数据输出信号的逻辑转换。停用电路被配置为在启用之后的延迟处停用输出电路。锁存器耦合到输出电路,并且其被配置为响应于输出电路的激活而改变锁存器输出状态。锁存器被配置为在停用输出电路之后保持输出节点的状态。输入电路被配置为取决于时钟信号来激活输出电路。停用电路被配置为与时钟信号无关地停用输出电路。

著录项

  • 公开/公告号US2011254669A1

    专利类型

  • 公开/公告日2011-10-20

    原文格式PDF

  • 申请/专利权人 ANAND DIXIT;ROBERT P. MASLEID;

    申请/专利号US20100759833

  • 发明设计人 ANAND DIXIT;ROBERT P. MASLEID;

    申请日2010-04-14

  • 分类号G08B1/00;

  • 国家 US

  • 入库时间 2022-08-21 18:16:33

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