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Latch circuit tolerant to single event transient
Latch circuit tolerant to single event transient
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机译:锁存电路可承受单事件瞬变
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摘要
A latch circuit has: a data input unit to which an input data is input; and a data retention unit including a node connected to the data input unit. The data input unit transmits a data depending on the input data to the node, when both of a first clock signal and a second clock signal that are driven independently from each other are at a first level. The data retention unit holds a data at the node, when at least one of the first clock signal and the second clock signal is at a second level that is an inverted level of the first level.
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