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Layered Modeling for High-Level Synthesis of Electronic Designs
Layered Modeling for High-Level Synthesis of Electronic Designs
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机译:电子设计高级综合的分层建模
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摘要
Methods and apparatuses for modeling and simulating a high-level circuit design are provided. With some implementations of the invention, a layered model corresponding to an algorithmic description for a circuit design is generated. The layered model includes a set of threads that describe the behavior of the circuit design, a schedule that describes timing constraints of the circuit design, and interfaces that facilitate the transfer of data between various layered models. With some implementations, a layered model may also include a shared variable that facilitates the transfer of data between ones of the set of threads within a layered model.
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