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Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices

机译:用于调整可编程逻辑器件的性能特征和功耗的设备和方法

摘要

A PLD includes at least one IP block or circuit, and at least one I/O block or circuit. The performance of the at least one IP block is adjusted in order to meet at least one performance characteristic by changing a supply level of the at least one IP block, by adjusting at least one body bias level of the IP block, or both. The performance of the at least one I/O block is adjusted by changing a supply level of the at least one I/O block, by adjusting at least one body bias level of the I/O block, or both.
机译:PLD包括至少一个IP块或电路,以及至少一个I / O块或电路。调整至少一个IP块的性能以便通过改变至少一个IP块的供电水平,通过调整IP块的至少一个本体偏置水平或两者来满足至少一个性能特征。至少一个I / O块的性能通过改变至少一个I / O块的供电水平,通过调节I / O块的至少一个本体偏置水平或两者来调节。

著录项

  • 公开/公告号US7986160B2

    专利类型

  • 公开/公告日2011-07-26

    原文格式PDF

  • 申请/专利权人 TIM TRI HOANG;SERGEY SHUMARAYEV;

    申请/专利号US20060420737

  • 发明设计人 TIM TRI HOANG;SERGEY SHUMARAYEV;

    申请日2006-05-27

  • 分类号H03K17/16;H03K19/173;

  • 国家 US

  • 入库时间 2022-08-21 18:10:42

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