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Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension
Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension
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机译:利用数字信号处理器块存储器扩展实现乘法器的方法和装置
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摘要
A method for performing multiplication on a field programmable gate array includes generating a product by multiplying a first plurality of bits from a first number and a first plurality of bits from a second number. A stored value designated as a product of a second plurality of bits from the first number and a second plurality of bits from the second number is retrieved. The product is scaled with respect to a position of the first plurality of bits from the first number and a position of the first plurality of bits from the second number. The stored value is scaled with respect to a position of the second plurality of bits from the second number and a position of the second plurality of bits from the second number. The scaled product and the scaled stored value are summed.
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