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Apparatus and method for performing efficient multiply-accumulate operations in microprocessors
Apparatus and method for performing efficient multiply-accumulate operations in microprocessors
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机译:在微处理器中执行有效的乘法累加运算的设备和方法
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摘要
An apparatus for performing multiply-accumulate operations in a microprocessor comprising operand input registers for receiving data to be operated on an adder and a multiplier for performing operations on the data, a result output port for presenting results to the microprocessor, a multiplexer for storing results, an accumulator cache for storing an accumulator value internal to the apparatus, and control circuitry for controlling the operation of the apparatus.
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