A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and memory subsystems and an I/O controller coupled with the processor interconnect. The I/O controller may comprise a plurality of DMA read request queues, a DMA read slot pool comprising a plurality of DMA read slots, and an expander logic determining a priority of requests in said request queues.
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机译:在一个方面,一种用于支持推挽式DMA读取操作的I / O控制器-处理器互连耦合的系统可以包括:处理器互连,其包括多个高速缓存和存储器子系统;以及I / O控制器,其与处理器互连耦合。 I / O控制器可以包括多个DMA读取请求队列,包括多个DMA读取时隙的DMA读取时隙池以及确定所述请求队列中的请求优先级的扩展器逻辑。
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