Tri-core architecture for reducing MAC layer processing latency in base stations

摘要

A tri-core architecture for reducing MAC layer processing latency at the base stations is described. The new architecture minimizes the processing delay by introducing a pipelined approach. The fundamental concept involves splitting the Medium Access Control (MAC) layer functionality into three distinct tasks, with each processor performing a given task. All tasks will be thus performed concurrently, avoiding much of the overhead encountered while processing received packets and preparing packets to be transmitted.