首页>
外国专利>
Timing analysis of a mapped logic design using physical delays
Timing analysis of a mapped logic design using physical delays
展开▼
机译:使用物理延迟的映射逻辑设计的时序分析
展开▼
页面导航
摘要
著录项
相似文献
摘要
Approaches for determining a static timing analysis of a logic design are disclosed. Physical delay arcs of a plurality of physical elements of an integrated circuit specify respective propagation delays from inputs of the physical elements to outputs of the physical elements. Logic components of the logic design are mapped to selected ones of the physical components of the physical elements. For each of the logic components, the logic delay arcs are determined from the physical delay arcs. Each logic delay arc for each logic component specifies a propagation delay from an input of the logic component to an output of the logic component. A static timing analysis of the logic components is performed using the logic delay arc, and data from the timing analysis is output.
展开▼