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ADC HAVING IMPROVED SAMPLE CLOCK JITTER PERFORMANCE
ADC HAVING IMPROVED SAMPLE CLOCK JITTER PERFORMANCE
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机译:ADC的采样时钟抖动性能得到改善
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摘要
In conventional analog-to-digital converter (ADC) systems, jitter can be a problem because of delay circuits within the sample signal path. Here, an ADC system is provided with a modified delay locked loop (DLL), namely having a variable delay and a fixed delay. The modification to the delay line of DLL enables the removal of delay circuits from the sample path, improve the overall signal to noise ration (SNR).
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