首页> 外国专利> BANK STRUCTURE OF A FPGA BOARD MINIMIZING FOR SEMICONDUCTOR CERTIFICATION, CAPABLE OF MINIMIZING THE DISTANCE BETWEEN AN ARBITRARY SECTION AFTER AN IO PIN IS DIVIDED AND A CONNECTOR CONNECTED TO THE SECTION

BANK STRUCTURE OF A FPGA BOARD MINIMIZING FOR SEMICONDUCTOR CERTIFICATION, CAPABLE OF MINIMIZING THE DISTANCE BETWEEN AN ARBITRARY SECTION AFTER AN IO PIN IS DIVIDED AND A CONNECTOR CONNECTED TO THE SECTION

机译:最小化用于半导体认证的FPGA板的存储区结构,能够在分配IO引脚并将连接器连接到该部分后最小化任意部分之间的距离

摘要

PURPOSE: A bank structure is provided to effectively form a board by minimizing a pattering wiring.;CONSTITUTION: An FPGA board(100) is composed of a FPGA device(110) and a connector(200). The FPGA device has a logic circuit in order to verify a semiconductor. A plurality of connectors output and input a signal to the embedded FPGA device. A plurality of input/output pins are divided into an arbitrary number and are allocated into a plurality of regions. The connector is allocated to a plurality of regions.;COPYRIGHT KIPO 2011
机译:目的:提供了一种排样结构,以通过最小化图案布线来有效地形成板。;组成:FPGA板(100)由FPGA器件(110)和连接器(200)组成。 FPGA器件具有逻辑电路以便验证半导体。多个连接器输出信号并将信号输入到嵌入式FPGA器件。多个输入/输出引脚被划分为任意数量,并且被分配为多个区域。连接器分配到多个区域。; COPYRIGHT KIPO 2011

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